USING VERILOG IN MODELSIM

#1) Build a module that counts clock pulses (the clock is clk, use positive edges). It should take clk, and reset as an inputs and output count which is a binary array of size that permits it to count up to 31, and the output carry. Use a parameter to set the size of arrays. Use Verilog not System Verilog. At 31 it should generate a carry, which is an output, and the count should be set to zero. It should continue to count. Module name is prob1, Inputs should be clk, reset, outputs should be count and carry, size parameter should be named Size

#2) Write a test bench module for the counter in problem 1. It should generate a clock signal, and it should dump the count on each clock cycle to a file showing it count up to 31 and then reset to 0. You may use a loop statement of your choice. The module should be named prob2, file handle should be fd, and the size parameter in the module call to prob 1 should be local parameter N in the test bench, and should be set in the module instance.