verilog for 4 bit counter code and testbench

1. synchronous counter

2. design 4bit up counter with active-high enable signal

3. and with active-low asynchrnous reset signal(when active-low reset='0' -> reset)

//verilog for 4 bit counter//

module count_4bit (clk, rst,dout); input clk, rst; output [3:0] dout; reg [3:0] dout; wire clk, rst; initial dout= 0; always @ (posedge clk) begin if (rst) dout<= 0; else begin if (dout!=4'b1111) dout<= dout+1; else dout<=0; end end endmodule

This is my code. Is it correct?pls help!!!