We assume that the logic blocks used to implement a processor's datapath have the following latencies:

$\backslash$table$[[$Component$,$Latency $($ns$),$Component.,Latency $($ns$)],[$Instrrnction$/$Dala meinory,$225,$Register File,$125],[$Multiplexer$,20,$ALU,$175],[$Adder$,125,$Single gate,$7],[$Register read,$25,$Register setup,$20],[$Sign extend,$60,$Comtrol,$60]]$

Register read is the time necded after the rising clock edge for the new register value to appear on the out.put. This value applies to the PC only. Register setup is the annuut of time a register's data input must be stable before the rising edge of the clock. This value applies to both the PC and Register File.

a$.$ What is the latency of an R$-$type instruction $($i$.$e$.,$ how long must the clock period be to ensure that this instruction works correctly$)?$

b$.$ What is the latency of ld$?($Check your answer carelully: Many students place extra muxes on the critical path.$)$

c$.$ What is the latericy of beq?

d$.$ What is the minimum cluck period for this CPU?