Question: verilog hdl code for 4 bit word input and two single bit output divBy 3 and divBy 5 . divBy 3 is 1 if the

verilog hdl code for 4bit word input and two single bit output divBy3 and divBy5. divBy3 is 1 if the 4bit input is divisible by 3.
divBy5 is 1 if the 4bit input is divisible by 5

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