Verilog Test Fixture

I need help creating a verilog test fixture for my digital logic and assembly programming course

Create a Verilog Test Fixture named ALU_Decoder_Tester

.Use the table below for your test cases

(all input/output values are in binary)

Test Case Inputs Output

ALUOp Funct ALUControl

0 00 XXXXXX 010

1 01 XXXXXX 110

2 10 XX0000 010

3 10 XX0010 110

4 10 XX0100 000

5 10 XX0101 001

6 10 XX1010 111

Sample code for Test C ase 0 is shown below for reference

// Test Case 0

ALUOp = 2'b0;

Funct = 6'bX;

#10;

Be sure to use the $stop; system call after the last test case!