[Verilog] Write the testbench to simulate the behaviours of module mymem:

1. To describe an inferred RAM in Verilog, there have some following signals:

• clk: clock;
• rdata: output read data from RAM;
• address: read/write address;
• wdata: data that will be write to RAM;
• wen: allow to the wdata write to RAM at address.

2. Describe RAM as an array.
3. Read/write activity have to be triggered by a clock. Reset/Set is not allowed when using RAM.
4. The direct output of RAM have to be captured by a register before assign to rdata. Otherwise, RAM is not infered

To know your RAM design inferred successfully. Synthesize then look at "Design Run" tab in Vivado, if the value at the column "BRAM" or "URAM" is higher than 0, it means there are RAM that is inferrred.

1 module mymem (clk, rdata, addr, wen, wdata); 2 3 input clk; 4 output [31:0] rdata; 5 input [9:0] addr; 6 input wen; 7 input [31:0] wdata; reg [31:0]mem[0:1023]; reg [31:0]rdout; always @(posedge clk) begin if (wen) mem[addr]