VHDL Code

Design a Shifter unit that will perform both an arithmetic shift and a logical shift of a 32-bit binary number depending on the shift mode. The shift should be identified as right or left for a certain number of given bits. Then design a test bench to verify the correctness of the design. Include enough test cases to cover all possibilities. The block diagram of this component is as below: Shift Mode Shift Direction Shift Mode: shift mode (arithmetic or logical shift) Data Out(31:0)Nbr_of_Bit: number of bits will be shifed Nbr of_Bit(4:0) 32-bits Shifter Shift Direction: Shift left or right Data_In(31:0) The interface can be as below: entity ShifterUnit_32Bits_Design is port Shift Mode: Shift_Direction: in std_logic; Data In: Data_Out: in std_logic; Nbr of_Bit: in std_logic_vector (4 downto 0) in std_logic_vector (31 downto 0) out std_logic_vector (31 downto 0) end ShifterUnit_32Bits_Design; Design a Shifter unit that will perform both an arithmetic shift and a logical shift of a 32-bit binary number depending on the shift mode. The shift should be identified as right or left for a certain number of given bits. Then design a test bench to verify the correctness of the design. Include enough test cases to cover all possibilities. The block diagram of this component is as below: Shift Mode Shift Direction Shift Mode: shift mode (arithmetic or logical shift) Data Out(31:0)Nbr_of_Bit: number of bits will be shifed Nbr of_Bit(4:0) 32-bits Shifter Shift Direction: Shift left or right Data_In(31:0) The interface can be as below: entity ShifterUnit_32Bits_Design is port Shift Mode: Shift_Direction: in std_logic; Data In: Data_Out: in std_logic; Nbr of_Bit: in std_logic_vector (4 downto 0) in std_logic_vector (31 downto 0) out std_logic_vector (31 downto 0) end ShifterUnit_32Bits_Design