VHDL Code

Q3: Design a circuit that receives only "clock_50" as the input clock and "Key(0)" as the power-up reset and outputs a periodic (or clock) signal, "out_clock" with a selectable frequency. The SW(I downto 0) will be used to select the desired "out clock" frequency as shown in the table below. Draw a detailed schematic of your circuit. Submit VHDL codes (HW2Q3.vhd). a. b. SW(1 downto 0) Frequency of Out clock 1Hz 100Hz 10KHz MHz 01 10 Key(0) Clock 50 Out clock Q3: Design a circuit that receives only "clock_50" as the input clock and "Key(0)" as the power-up reset and outputs a periodic (or clock) signal, "out_clock" with a selectable frequency. The SW(I downto 0) will be used to select the desired "out clock" frequency as shown in the table below. Draw a detailed schematic of your circuit. Submit VHDL codes (HW2Q3.vhd). a. b. SW(1 downto 0) Frequency of Out clock 1Hz 100Hz 10KHz MHz 01 10 Key(0) Clock 50 Out clock