VHDL help. can someone please help answer this problem

Draw a block diagram that corresponds to the following VHDL model. Be sure to label all inputs, outputs, internal signals, and component ports. LIBRARY ieee; USE ieee.std_logic_l164.ALL; ENTITY circuit IS PORT(init, run, slow_pace, fast_pace, speed_sel: IN std_logic pump1, pump0, motorA, motorB: OUT std_logic); END Entity circuit; ARCHITECTURE problem OF circuit IS component counter_2bit is PORT (reset, en, clk: in std_logic; Q: out std_logic_vector(1 downto 0)); end component counter_2bit; component decode_2_to_4 is PORT (sel: in std_logic_vector(1 downto 0); D0, Dl, D2, D3: out std_logic); end component decode_2_to_4; signal clock: std_logic; signal S: std_logic_vector(1 downto 0); BEGIN cnt: counter_2bit port map (init, run, clock, S); dec: decode_2_to_4 port map (S, pump0, pump1, motorA, motorB); clock