Question: We have a standard 32-bit byte-addressed MIPS machine with 4 GiB RAM, a 4-way set-associative CPU data cache that uses 32 byte blocks, a LRU

We have a standard 32-bit byte-addressed MIPS machine with 4 GiB RAM, a 4-way set-associative CPU data cache that uses 32 byte blocks, a LRU replacement policy, and has a total capacity of 16 KiB. Consider the following C code and answer the questions below. (size of int type variable is 4 byte)

We have a standard 32-bit byte-addressed MIPS machine with 4 GiB RAM,

Lets say that we increase our CPU cache associativity to 8-way. What is our cache hit rate now? (answer in percentage with % sign, eg 10%)

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