WRITE A GATE MODELING $\{$AVOIDE USEING ASSIGN AND ALWAYS$]$

$//$ This is going to be $+$ve edge clock triggered register file.

$//$ Reset on RST$=0$

module REGISTER$\_$FILE$\_32$x$32($DATA$\_$R$1,$ DATA$\_$R$2,$ ADDR$\_$R$1,$ ADDR$\_$R$2,$

DATA$\_$W$,$ ADDR$\_$W$,$ READ, WRITE, CLK$,$ RST$)$;

$//$ input list

input READ, WRITE, CLK$,$ RST;

input $[`$DATA$\_$INDEX$\_$LIMIT:$0]$ DATA$\_$W;

input $[`$REG$\_$ADDR$\_$INDEX$\_$LIMIT:$0]$ ADDR$\_$R$1,$ ADDR$\_$R$2,$ ADDR$\_$W;

$//$ output list

output $[`$DATA$\_$INDEX$\_$LIMIT:$0]$ DATA$\_$R$1$;

output $[`$DATA$\_$INDEX$\_$LIMIT:$0]$ DATA$\_$R$2$;

$//$ TBD

endmodule

$//$ memory data file $($do not edit the following line $-$ required for mem load use$)$

$//$ instance$=/$RF$\_$TB$/$result

$//$ format$=$hex addressradix$=$h dataradix$=$h version$=1\mathrm{.}0$ wordsperline$=1$ noaddress

$00000000$

$00000000$

$00000001$

$00000001$

$00000002$

$00000002$

$00000003$

$00000003$

$00000004$

$00000004$

$00000005$

$00000005$

$00000006$

$00000006$

$00000007$

$00000007$

$00000008$

$00000008$

$00000009$

$00000009$

$0000000$a

$0000000$a

$0000000$b

$0000000$b

$0000000$c

$0000000$c

$0000000$d

$0000000$d

$0000000$e

$0000000$e

$0000000$f

$0000000$f

$00000010$

$00000010$

$00000011$

$00000011$

$00000012$

$00000012$

$00000013$

$00000013$

$00000014$

$00000014$

$00000015$

$00000015$

$00000016$

$00000016$

$00000017$

$00000017$

$00000018$

$00000018$

$00000019$

$00000019$

$0000001$a

$0000001$a

$0000001$b

$0000001$b

$0000001$c

$0000001$c

$0000001$d

$0000001$d

$0000001$e

$0000001$e

$0000001$f

$0000001$f