$\{$USE GATE MODELING and, nand, or$,$ etc$\}$

$\text{'}\text{'}\text{'}\text{'}\text{'}\text{'}\text{'}\text{'}\text{'}\text{'}\text{'}\text{'}\text{'}\text{'}\text{'}[$DO NOT DO NOT USE assign and always$]\text{'}\text{'}\text{'}\text{'}\text{'}\text{'}\text{'}\text{'}\text{'}\text{'}$

Objective:To implement a Verilog gate level model for $32$x$32-$bit register file $.$

Outcome:Gate level implementation for the following components.

DECODER$\_5$x$32$MUX$32\_32$x$1$REGISTER$\_$FILE$\_32$x$32$

Complete gate level description of$$ following components in mux.v$$

MUX$32\_32$x$1$

Complete gate level description of$$ following components in logic.v

DECODER$\_2$x$4$DECODER$\_3$x$8$DECODER$\_4$x$16$DECODER$\_5$x$32$

Complete gate level description of$$ following components in register$\_$file.v

REGISTER$\_$FILE$\_32$x$32$

Compile entire Project$03$ and simulate following modules in$$ ModelSim simulator.

MUX$32\_32$x$1\_$TBDECODER$\_5$x$32\_$TBRF$\_$TB

Observe corresponding outcomes$$ on waveform windows and fix any issue.

Each testbench will generate corresponding output file.

OUTPUT$/$mux$32\_32$x$1\_$tb$.$outOUTPUT$/$decoder$\_5$x$32\_$tb$.$outOUTPUT$/$rf$\_$tb$.$out

$//32-$bit mux

module MUX$32\_32$x$1($Y$,$ I$0,$ I$1,$ I$2,$ I$3,$ I$4,$ I$5,$ I$6,$ I$7,$

I$8,$ I$9,$ I$10,$ I$11,$ I$12,$ I$13,$ I$14,$ I$15,$

I$16,$ I$17,$ I$18,$ I$19,$ I$20,$ I$21,$ I$22,$ I$23,$

I$24,$ I$25,$ I$26,$ I$27,$ I$28,$ I$29,$ I$30,$ I$31,$ S$)$;

$//$ output list

output $[31$:$0]$ Y;

$//$input list

input $[31$:$0]$ I$0,$ I$1,$ I$2,$ I$3,$ I$4,$ I$5,$ I$6,$ I$7$;

input $[31$:$0]$ I$8,$ I$9,$ I$10,$ I$11,$ I$12,$ I$13,$ I$14,$ I$15$;

input $[31$:$0]$ I$16,$ I$17,$ I$18,$ I$19,$ I$20,$ I$21,$ I$22,$ I$23$;

input $[31$:$0]$ I$24,$ I$25,$ I$26,$ I$27,$ I$28,$ I$29,$ I$30,$ I$31$;

input $[4$:$0]$ S;

$//$ TBD

endmodule

$//5$x$32$ Line decoder

module DECODER$\_5$x$32($D$,$I$)$;

$//$ output

output $[31$:$0]$ D;

$//$ input

input $[4$:$0]$ I;

$//$ TBD

endmodule

$//4$x$16$ Line decoder

module DECODER$\_4$x$16($D$,$I$)$;

$//$ output

output $[15$:$0]$ D;

$//$ input

input $[3$:$0]$ I;

$//$ TBD

endmodule

$//3$x$8$ Line decoder

module DECODER$\_3$x$8($D$,$I$)$;

$//$ output

output $[7$:$0]$ D;

$//$ input

input $[2$:$0]$ I;

$//$TBD

endmodule

$//2$x$4$ Line decoder

module DECODER$\_2$x$4($D$,$I$)$;

$//$ output

output $[3$:$0]$ D;

$//$ input

input $[1$:$0]$ I;

$//$ TBD

endmodule

$`$include $"$prj$\_$definition.v$"$

$//$ This is going to be $+$ve edge clock triggered register file.

$//$ Reset on RST$=0$

module REGISTER$\_$FILE$\_32$x$32($DATA$\_$R$1,$ DATA$\_$R$2,$ ADDR$\_$R$1,$ ADDR$\_$R$2,$

DATA$\_$W$,$ ADDR$\_$W$,$ READ, WRITE, CLK$,$ RST$)$;

$//$ input list

input READ, WRITE, CLK$,$ RST;

input $[`$DATA$\_$INDEX$\_$LIMIT:$0]$ DATA$\_$W;

input $[`$REG$\_$ADDR$\_$INDEX$\_$LIMIT:$0]$ ADDR$\_$R$1,$ ADDR$\_$R$2,$ ADDR$\_$W;

$//$ output list

output $[`$DATA$\_$INDEX$\_$LIMIT:$0]$ DATA$\_$R$1$;

output $[`$DATA$\_$INDEX$\_$LIMIT:$0]$ DATA$\_$R$2$;

$//$ TBD

endmodule

$//$ memory data file $($do not edit the following line $-$ required for mem load use$)$

$//$ instance$=/$MUX$32\_32$x$1\_$TB$/$result

$//$ format$=$hex addressradix$=$h dataradix$=$h version$=1\mathrm{.}0$ wordsperline$=1$ noaddress

$00000000$

$00000001$

$00000002$

$00000003$

$00000004$

$00000005$

$00000006$

$00000007$

$00000008$

$00000009$

$0000000$a

$0000000$b

$0000000$c

$0000000$d

$0000000$e

$0000000$f

$00000010$

$00000011$

$00000012$

$00000013$

$00000014$

$00000015$

$00000016$

$00000017$

$00000018$

$00000019$

$0000001$a

$0000001$b

$0000001$c

$0000001$d

$0000001$e

$0000001$f

$//$ memory data file $($do not edit the following line $-$ required for mem load use$)$

$//$ instance$=/$DECODER$\_5$x$32\_$TB$/$result

$//$ format$=$bin addressradix$=$h dataradix$=$b version$=1\mathrm{.}0$ wordsperline$=1$ noaddress

$00000000000000000000000000000001$

$00000000000000000000000000000010$

$00000000000000000000000000000100$

$00000000000000000000000000001000$

$00000000000000000000000000010000$

$00000000000000000000000000100000$

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