Question: { USE GATE MODELING } ' ' ' ' DO NOT USE ALWAYS and ANYWAYS Objective: To implement a Verilog gate level model for 3

{USE GATE MODELING}
''''DO NOT USE ALWAYS and ANYWAYS
Objective: To implement a Verilog gate level model for 32-bit register.
Outcome:Gate level implementation for the following components.
SR_LATCHD_LATCHD_FFREG1REG32
Instruction: Complete gate level description of following components in logic.v file.
SR_LATCHD_LATCH D_FFREG1REG32
Compile entire Project03 and simulate following modules in ModelSim simulator.
SR_LATCH_TBD_LATCH_TBD_FF_TBREG1_TBREG32_TB
Observe corresponding outcomes on waveform windows and fix any issue.
Each testbench will generate corresponding output file.
OUTPUT/sr_latch_tb.outOUTPUT/d_latch_tb.outOUTPUT/d_ff_tb.outOUTPUT/d_reg1_tb.outOUTPUT/d_reg32_tb.out
This should match with corresponding golden output file in CS147-Project03/GOLDEN/directory.
sr_latch_tb.out.goldend_latch_tb.out.goldend_ff_tb.out.goldend_reg1_tb.out.goldend_reg32_tb.out.golden
Add more testing in these testbenches to make sure outcome is correct.
//32-bit registere +ve edge, Reset on RESET=0
module REG32(Q, D, LOAD, CLK, RESET);
output [31:0] Q;
input CLK, LOAD;
input [31:0] D;
input RESET;
// TBD
endmodule
//1 bit register +ve edge,
// Preset on nP=0, nR=1, reset on nP=1, nR=0;
// Undefined nP=0, nR=0
// normal operation nP=1, nR=1
module REG1(Q, Qbar, D, L, C, nP, nR);
input D, C, L;
input nP, nR;
output Q,Qbar;
// TBD
endmodule
//1 bit flipflop +ve edge,
// Preset on nP=0, nR=1, reset on nP=1, nR=0;
// Undefined nP=0, nR=0
// normal operation nP=1, nR=1
module D_FF(Q, Qbar, D, C, nP, nR);
input D, C;
input nP, nR;
output Q,Qbar;
// TBD
endmodule
//1 bit D latch
// Preset on nP=0, nR=1, reset on nP=1, nR=0;
// Undefined nP=0, nR=0
// normal operation nP=1, nR=1
module D_LATCH(Q, Qbar, D, C, nP, nR);
input D, C;
input nP, nR;
output Q,Qbar;
// TBD
endmodule
//1 bit SR latch
// Preset on nP=0, nR=1, reset on nP=1, nR=0;
// Undefined nP=0, nR=0
// normal operation nP=1, nR=1
module SR_LATCH(Q,Qbar, S, R, C, nP, nR);
input S, R, C;
input nP, nR;
output Q,Qbar;
// TBD
endmodule

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