Question: Write a Verilog code for Half Adder using Gate Level modeling. Write a Verilog code for Full Adder using Gate Level modeling. Write a Verilog

Write a Verilog code for Half Adder using Gate Level modeling. Write a Verilog code for Full Adder using Gate Level modeling. Write a Verilog code for Half Subtractor using Gate Level modeling. Write a Verilog code for Adder and Subtractor using Gate Level modeling.

Need code and output for all the problems using Modelsim

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