Write a VHDL code that makes a 8+n mod counter/timer where n is the last digit of your student number.

-The timer has two pushbutton inputs, reset_n and run_stop. It has one 4-bit output, seconds that drives LED's and one-bit output alarm that drives one LED.

-The time can be in one of two states: run=0 and run=1

- run is set to 0 when reset_n is asserted; it set to the logical inverse of run (not run) when there is a rising edge of run_stop.

-seconds, the time remaining, is set to the initial timer value when reset_n is asserted; it is decremented by 1 once per second when run=1 and seconds /= 0 (that is when the timer is running and there is still time remaining).

- The alarm LED is turned on when run=1 and the time remaining is zero.

-The initial time remaining should be 8+(n mod 8) seconds where n is the the last digit of your student number. For example, if your ID is 0221 then n=1 and the timer will count from, 8+(1 mod 8) = 8+1 = 8. The timer should count from 9 seconds to 0.

-The design should be synchronous- all registers should use the same clock and not use asynchronous sets or clears. In particular, reset_n does not directly clear any registers, it is used to determine the value loaded into the registers on the next rising edge of clock.

-the clock for the design will use a 50MHz oscillator built in the cpld

The timer should count from 9-0 (as mentioned above)

Modeling Registers It is common to use one signal name for the input and one for output of a register. For example, if the output of a register is called count, the signal count_next would be its input: signal count, count_next : unsigned(3 downto); or count_next