Write a VHDL code using processes for the following logic circuit which include a shift register and 4x1 multiplexer. Use the entity below.

entity registers_min_max is port( din : in std_logic_vector(3 downto 0); reset : in std_logic; clk : in std_logic; sel : in std_logic_vector(1 downto 0); reg_out : out std_logic_vector(3 downto 0)); end registers_min_max;

din reset RO clk reset R1 A C clk reset R2 clk reset R3 clk 3 0 sel LE