Question: Write a VHDL module with inputs clk and reset (not shown in the timing diagram), and outputs: output1 and output2. You may choose active-low or

Write a VHDL module with inputs clk and reset (not shown in the timing diagram), and outputs: output1 and output2. You may choose active-low or active-high reset, but the master reset will force the internal count back to 0. Signal count is internal just for describing the behavior of this circuit.

clk outp output2

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