Question: Write a Xilinx Constraints file which will add the following constraints: 1. Lock your clk to pin Y9 and rst to pin W10. The 5

Write a Xilinx Constraints file which will add the following constraints: 1. Lock your clk to pin Y9 and rst to pin W10. The 5 bits of your output should be driven out on pins W13, W15, W16, W17 and W18. 2. Sets I/O Standard as LVCMOS18 for all the I/O pins. 3. Specify input clock frequency as 100MHz.

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