Question: Write an SystemVerilog module for a JK flip-flop. The flip-flop has input port: clk, J, and K, and output port: Q. On the rising edge

Write an SystemVerilog module for a JK flip-flop. The flip-flop has input port: clk, J, and K, and output port: Q. On the rising edge of the clock, Q keeps its old value if J = K = 0. It sets Q to 1 if J = 1, resets Q to 0 if K = 1, and inverts Q if J = K = 1.

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