Question: Write code in verilog to represet a 32 bit ALU that can Select Operation Signed Addition Signed Subtraction Bitwise AND Bitwise OR 01 10 This

Write code in verilog to represet a 32 bit ALU that can

Select Operation Signed Addition Signed Subtraction Bitwise AND Bitwise OR 01 10 This module has three inputs: two 32-bit signed numbers represented in 2's complement format (A and B) and a 2-bit control (SELECT). It produces a 32-bit result (R). You are required to provide the Verilog code for the ALU

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