write me a code that gives this output $//$ memory data file $($do not edit the following line $-$ required for mem load use$)//$ instance$=/$DA$\_$VINCI$\_$TB$/$da$\_$vinci$\_$inst$/$memory$\_$inst$/$sram$\_32$x$64$m $//$ format$=$hex addressradix$=$h dataradix$=$h version$=1\mathrm{.}0$ wordsperline$=1$ noaddress $00000020000000200000001000000010000000090000000800000008000000050000000400000002//$ memory data file $($do not edit the following line $-$ required for mem load use$)//$ instance$=/$DA$\_$VINCI$\_$TB$/$da$\_$vinci$\_$inst$/$memory$\_$inst$/$sram$\_32$x$64$m $//$ format$=$hex addressradix$=$h dataradix$=$h version$=1\mathrm{.}0$ wordsperline$=1$ noaddress $000000010000000400000004000000100000001000000000//$ memory data file $($do not edit the following line $-$ required for mem load use$)//$ instance$=/$DA$\_$VINCI$\_$TB$/$da$\_$vinci$\_$inst$/$memory$\_$inst$/$sram$\_32$x$64$m $//$ format$=$hex addressradix$=$h dataradix$=$h version$=1\mathrm{.}0$ wordsperline$=1$ noaddress $000000000000002000000008000000080000000200000002//$ memory data file $($do not edit the following line $-$ required for mem load use$)//$ instance$=/$DA$\_$VINCI$\_$TB$/$da$\_$vinci$\_$inst$/$memory$\_$inst$/$sram$\_32$x$64$m $//$ format$=$hex addressradix$=$h dataradix$=$h version$=1\mathrm{.}0$ wordsperline$=1$ noaddress $0000001500000017000000190000001$b $0000001$d $0000001$f $0000002100000023000000250000002500000000//$ memory data file $($do not edit the following line $-$ required for mem load use$)//$ instance$=/$DA$\_$VINCI$\_$TB$/$da$\_$vinci$\_$inst$/$memory$\_$inst$/$sram$\_32$x$64$m $//$ format$=$hex addressradix$=$h dataradix$=$h version$=1\mathrm{.}0$ wordsperline$=1$ noaddress $000000000000000100000001000000020000000300000005000000080000000$d $0000001500000022000000370000005900000090000000$e$90000017900000262//$ memory data file $($do not edit the following line $-$ required for mem load use$)//$ instance$=/$DA$\_$VINCI$\_$TB$/$da$\_$vinci$\_$inst$/$memory$\_$inst$/$sram$\_32$x$64$m $//$ format$=$hex addressradix$=$h dataradix$=$h version$=1\mathrm{.}0$ wordsperline$=1$ noaddress ffffffc$900000022$ ffffffeb $0000000$d fffffff$800000005$ fffffffd $00000002$ ffffffff $00000001000000000000000100000001000000020000000300000005$

$`$include $"$prj$\_$definition.v$"$

module CONTROL$\_$UNIT$($MEM$\_$DATA, RF$\_$DATA$\_$W$,$ RF$\_$ADDR$\_$W$,$ RF$\_$ADDR$\_$R$1,$ RF$\_$ADDR$\_$R$2,$ RF$\_$READ, RF$\_$WRITE,

ALU$\_$OP$1,$ ALU$\_$OP$2,$ ALU$\_$OPRN, MEM$\_$ADDR, MEM$\_$READ, MEM$\_$WRITE,

RF$\_$DATA$\_$R$1,$ RF$\_$DATA$\_$R$2,$ ALU$\_$RESULT, ZERO, CLK$,$ RST$)$;

$//$ Output signals

$//$ Outputs for register file

output $[`$DATA$\_$INDEX$\_$LIMIT:$0]$ RF$\_$DATA$\_$W;

output $[`$ADDRESS$\_$INDEX$\_$LIMIT:$0]$ RF$\_$ADDR$\_$W$,$ RF$\_$ADDR$\_$R$1,$ RF$\_$ADDR$\_$R$2$;

output RF$\_$READ, RF$\_$WRITE;

$//$ Outputs for ALU

output $[`$DATA$\_$INDEX$\_$LIMIT:$0]$ ALU$\_$OP$1,$ ALU$\_$OP$2$;

output $[`$ALU$\_$OPRN$\_$INDEX$\_$LIMIT:$0]$ ALU$\_$OPRN;

$//$ Outputs for memory

output $[`$ADDRESS$\_$INDEX$\_$LIMIT:$0]$ MEM$\_$ADDR;

output MEM$\_$READ, MEM$\_$WRITE;

$//$ Input signals

input $[`$DATA$\_$INDEX$\_$LIMIT:$0]$ RF$\_$DATA$\_$R$1,$ RF$\_$DATA$\_$R$2,$ ALU$\_$RESULT;

input ZERO, CLK$,$ RST;

$//$ Inout signal

inout $[`$DATA$\_$INDEX$\_$LIMIT:$0]$ MEM$\_$DATA;

$//$ State nets

wire $[2$:$0]$ proc$\_$state;

PROC$\_$SM state$\_$machine$(.$STATE$($proc$\_$state$),.$CLK$($CLK$),.$RST$($RST$))$;

always @ $($proc$\_$state$)$

begin

$//$ TBD: Code for the control unit model

end

task print$\_$instruction;

input $[`$DATA$\_$INDEX$\_$LIMIT:$0]$ inst;

reg $[5$:$0]$ opcode;

reg $[4$:$0]$ rs;

reg $[4$:$0]$ rt;

reg $[4$:$0]$ rd;

reg $[4$:$0]$ shamt;

reg $[5$:$0]$ funct;

reg $[15$:$0]$ immediate;

reg $[25$:$0]$ address;

begin

$//$ parse the instruction

$//$ R$-$type

$\{$opcode$,$ rs$,$ rt$,$ rd$,$ shamt, funct$\}=$ inst;

$//$ I$-$type

$\{$opcode$,$ rs$,$ rt$,$ immediate $\}=$ inst;

$//$ J$-$type

$\{$opcode$,$ address$\}=$ inst;

$write$("$@ $\%6$dns $->[0$X$\%08$h$]",$ $time, inst$)$;

case$($opcode$)$

$//$ R$-$Type

$6\text{'}$h$00$ : begin

case$($funct$)$

$6\text{'}$h$20$: $write$("$add r$\%02$d$,$ r$\%02$d$,$ r$\%02$d;$",$ rd$,$ rs$,$ rt$)$;

$6\text{'}$h$22$: $write$("$sub r$\%02$d$,$ r$\%02$d$,$ r$\%02$d;$",$ rd$,$ rs$,$ rt$)$;

$6\text{'}$h$2$c: $write$("$mul r$\%02$d$,$ r$\%02$d$,$ r$\%02$d;$",$ rd$,$ rs$,$ rt$)$;

$6\text{'}$h$24$: $write$("$and r$\%02$d$,$ r$\%02$d$,$ r$\%02$d;$",$ rd$,$ rs$,$ rt$)$;

$6\text{'}$h$25$: $write$("$or r$\%02$d$,$ r$\%02$d$,$ r$\%02$d;$",$ rd$,$ rs$,$ rt$)$;

$6\text{'}$h$27$: $write$("$nor r$\%02$d$,$ r$\%02$d$,$ r$\%02$d;$",$ rd$,$ rs$,$ rt$)$;

$6\text{'}$h$2$a: $write$("$slt r$\%02$d$,$ r$\%02$d$,$ r$\%02$d;$",$ rd$,$ rs