Write the Verilog code for a register file with two write ports, plus a test$-$bench. Include all of your Verilog code in a file named and upload it on Canvas.

RegisterFile$2$W$.$v

a$)(3$ pt$.)$ Write a Verilog module for the register file implemented in the previous question using a behavioral model. Besides the two write ports, add one single read port to the module, which will allow you to inspect the content of the registers in the test$-$bench of next question. The additional signals needed for the read port are:

$$Input read index $(5$ bits$)$: index of the register to read from. This signal operates synchronously $($i$.$e$.,$ regardless of the value of the clock signal$),$ and without any kind of additional enable signal $($i$.$e$.,$ the read port is always active$).$

$$Output read value $(32$ bits$)$: value read from the register.

b$)(3$ pt$)$ Write a Verilog test$-$bench for your register file implementation. Your test$-$bench should explore at least the following combinations of inputs, and verify the right output in each case:

$$Both write ports are active and write different values into different registers in the same cycle.

$$Both write ports are active and write different values into the same register in the same cycle.