You are given a binary mod $16$ counter that counts from $0-15$ with each clock pulse from an available clocking signal CLK$.$ QD is msb$,$ QA is lsb of the count. A$,$B$,$C$,$ & D are inputs $($A is lsb$,$ D is msb$)$ that can be loaded into the counter with the LOAD input. The counter also has a clear input $($CLR$)$ and a chip enable input $($EN$).$ Configure this counter, with minimal gates & smallest gates, to generate a count sequence of $8-12$ and repeats. The given table shows signal functionality. Draw the circuit and show ALL connections$/$signals$.(10)$