You are given the following RISC$-$V assembly code.

lw t$0,0($t$1)$

lw s$1,0($s$0)$

addi t$0,$ t$0,1$

add t$2,$ t$0,$ t$1$

add s$2,$ s$2,$ s$2$

addi s$1,$ s$1,1$

add s$3,$ s$2,$ s$1$ Suppose the code is executing on a RISC$-$V processor with a $5-$stage pipeline, without support for forwarding, but with support for hazard detection. The processor uses stall cycles $($nops$)$ to resolve data hazards. How many stall cycles $($nops$)$ will the code incur? How many cycles does the code take to execute on this processor? Assume execution starts with an empty pipeline. Suppose the code is executing on a RISC$-$V processor with a $5-$stage pipeline, with support for forwarding and hazard detection. How many stall cycles $($nops$)$ will the code incur? How many cycles does the code take to execute on this processor? Assume execution starts with an empty pipeline. What is the speedup of the processor with forwarding and hazard detection compared to the processor without forwarding? Round your answer to two digits.