Question: Consider the following MIPS assembly code: ADDI $17, $0, 10 ADD $18, $0, $0 LOOP: LW $8, 12($19) ADD $18, $18, $8 ADDI $17, $17,

Consider the following MIPS assembly code:

ADDI $17, $0, 10

ADD $18, $0, $0

LOOP:

LW $8, 12($19)

ADD $18, $18, $8

ADDI $17, $17, -1

SLT $9, $0, $17

BNE $9, $0, LOOP

ADDI $18, $18, 1

SW $18, 12($19)

During the pipeline cycle that evaluates whether the BRANCH instruction in your code will require any data to be forwarded to it, what is in each of the following pipeline registers?

ID/EX.RegisterRs?

ID/EX.RegisterRt?

EX/MEM.RegisterRd?

MEM/WB.RegisterRd?

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