You are using a $2-$way set$-$associative $L1$ cache with a capacity of $8KB$ and cache lines

consisting of $4$ words. The $L2$ cache has a latency of $10$ cycles for both read and write

operations. Here is the sequence of write operations performed on the cache, with each

entry representing a $32-$bit address in hexadecimal format:

$01000,01004,01010,011c0,02000,021c0,03400,03404,03f00,02004,$

$01004$

$($Please show detailed process or your will get $0$ point$)$

I.How many cache misses occur if an LRU policy is implemented? $(pt{s}_{?})$

II$.$If the cache size remains the same but is changed to a direct$-$mapped configuration, would

the miss$-$rate increase or decrease? Explain why? $(12$ pts$)$

III. What is the time duration for a read$-$miss eviction in a write$-$back, write$-$allocate cache? And

how about for a write$-$miss? $($Assuming the cache line is dirty$)(10$ pts$)$