You have a byte-addressable virtual memory system with a two-entry TLB, a 2-way set associative cache, and a page table for process P. Assume cache blocks of 8 bytes and page size of 16 bytes. In system below, main memory is divided into blocks, where each block is represented by a letter. Two blocks equal one frame.

Page	Frame
0	5
4	2
TLB

Page		Block
0	A	0
	B	1
1	C	2
	D	3
2	E	4
	F	5
3	G	6
	H	7
4	I	8
	J	9
5	K	10
	L	11
6	M	12
	N	13
7	O	14
	P	15
Virtual Memory for P

	TAG	DATA	TAG	DATA
Set 0	00	C	01	I
Set 1	00	D	10	H
	Cache

Frame		Block
0	C	0
	D	1
1	I	2
	J	3
2	G	4
	H	5
3	A	6
	B	7
Main Memory

	Frame	Valid
0	5	1
1	0	1
2	-	0
3	2	1
4	2	1
5	-	0
6	-	0
7	-	0
	Page Table

a.) Show the address format for virtual address 29₁₀ (specify field name and size) that would be used by the system to translate to a physical address and then translate this virtual address into the corresponding physical address. Explain how these fields are used to the corresponding physical addresses.

b.) Given Virtual address 0x06 converts to physical address 0x36. Show the format for a physical address that is used to determine the cache location for this address. Explain how to use this format to determine where physical address 0x36 would be located in cache.

c.) Given Virtual address 6₁₀ converts to physical address 54₁₀. Show the format for a physical address that is used to determine the cache location for this address. Explain how to use this format to determine where physical address 0x36 would be located in cache.

d.) Given Virtual address 0x19 is located on virtual page 1, offset 9. Indicate exactly how this address would be translated to its corresponding physical address and how the data would be accessed. Include in your explanation how the TLB, the page table, cache, and memory are used.