(a) For the system described in Problem P13.10, design a lag compensator Gc(s) using the methods of Chapter 10 to achieve an overshoot less than 30% and a steady-state error less than 0.01 for a ramp input. Assume a continuous non sampled system with Gp(s).
(b) Determine a suitable D(z) to satisfy the requirements of part (a) with a sampling period T = 0.1 s. Assume a zero-order hold and sampler, and use the Gc(s)-to-D(z) conversion method.
(c) Plot the step response of the system with the continuous- time compensator Gc(s) of part (a) and of the digital system with the D(z) of part (b). Compare the results.
(d) Repeat part (b) for T = 0.01 s and then repeat part (c).
(e) Plot the ramp response for D(z) with T = 0.1 s and compare it with the continuous-system response.