Repeat Problem 9.23, but skip the SPICE simulation. Here, M₉will be used in the op amp in Fig. 6.58. Let V_DD= V_SS= 1.5 V and I_S= 200 µA. Use L = 1 µm for all transistors, W₈= W₁₀= 150 µm, and W₁₁= W₁₂= 100 µm. Assume that X_d= 0.1 µm for all transistors operating in the active region, and use Table 2.4 for other parameters.

Table 2.4:

Value Value -Channel p-Channel Parameter Symbol Transistor Transistor Units NA. ND 5 x 105 Substrate doping 4 x 1016 Atoms/cm Gate oxide thickness 80 80 Metal-silicon work function -0.6 -0.1 cm?/V-s Channel mobility 450 150 Minimum drawn channel Len 0.4 0.4 length Source, drain junction depth Source, drain side diffusion Overlap capacitance per unit gate width Threshold adjust implant (box dist) , La Cal 0.15 0.18 0.09 0.09 0.35 0.35 T/m impurity type effective depth X; 0.16 0.16 3 x 1016 Atoms/cm effective surface 4 x 1016 concentration Nominal threshold voltage V, Napeiy -0.8 10 0.6 10 Polysilicon gate doping Atoms/cm concentration R, Cp Poly gate sheet resistance Source, drain-bulk junction capacitances (zero bias) Source, drain-bulk junction capacitance grading F/um? 0.2 0.4 0.5 0.4 coefficient C ja Source, drain periphery capacitance (zero bias) Source, drain periphery capacitance grading 1.2 2.4 T/m 0.4 0.3 coefficient Source, drain junction built-in potential 0.7 0.7 Oss Surface-state density 10! 10" Atoms/cm? dX4 Channel-length modulation 0.02 0.04 /V dVos parameter