Examine the difficulty of adding a proposed lwi.drd, rsl, rs2 (“Load With Increment”) instruction to MIPS.

Interpretation: Reg[rd] = Mem[Reg[rs1] + Reg[rs2]]

1. Which new functional blocks (if any) do we need for this instruction?

2. Which existing functional blocks (if any) require modification?

3. Which new data paths (if any) do we need for this instruction?

4. What new signals do we need (if any) from the control unit to support this instruction?