Examine the difficulty of adding a proposed ss rt, rs, imm (Store Sum) instruction to MIPS.

Interpretation: Mem[Reg[rt]=Reg[rs]+immediate

1. Which new functional blocks (if any) do we need for this instruction?

2. Which existing functional blocks (if any) require modification?

3. What new data paths do we need (if any) to support this instruction?

4. What new signals do we need (if any) from the control unit to support this instruction?

5. Modify Figure 4.21 to demonstrate an implementation of this new instruction.

Figure 4.21

PC Add Read address Instruction (31-01 Instruction [31-26] Instruction [25-21] Instruction [20-16] Instruction Instruction [15-11] memory Control Instruction [15-0] RegDst Branch MemRead MemtoReg ALUOP MemWrite ALUSro RegWrite Read register 1 Read data 1 Read register 2 Write Read register data 2 Write data Registers 16 Sign- extend 32 Instruction [5-0] Shift left 2, MUX ALU Add, result ALU control Zero ALU result ALU o Max Read data Address Data Write data memory MX