If it costs $1 to reduce the latency of a single component of the datapath by 1ps, what would it cost to reduce the clock cycle time by 20% in the single-cycle and in the pipelined design?

The remaining three problems in this exercise assume that components of the datapath have the following latencies:

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a. 1-Mem Add Mux ALU 200ps 70ps 20ps 90ps 200ps 50ps 250ps b. 750ps Regs D-Mem Sign-Extend 90ps 250ps 15ps 300ps 500ps 100ps Shift-Left-2 10ps 5ps