Question: If the processor has forwarding, but we forgot to implement the hazard detection unit, what happens when this code executes? This exercise is intended to

If the processor has forwarding, but we forgot to implement the hazard detection unit, what happens when this code executes?

This exercise is intended to help you understand the relationship between forwarding, hazard detection, and ISA design. Problems in this exercise refer to the following sequences of instructions, and assume that it is executed on a 5-stage pipelined datapath: a. b. ADD R5, R2, R1 LW R3,4 (R5) LW R2,0(R2) R3, R5, R3 OR SW R3,0(R5) LW R2,0 (R1) AND R1, R2, R1 LW

a. b. ADD R5, R2, R1 LW R3,4 (R5) LW R2,0(R2) R3, R5, R3 OR SW R3,0(R5) LW R2,0 (R1) AND R1, R2, R1 LW R3,0(R2) LW R1,0 (R1) R1,0 (R2) SW Instruction sequence

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In a 5stage pipelined processor the stages typically include Instruction Fetch IF Instruction Decode ID Execute EX Memory Access MEM and Write Back WB ... View full answer

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