What would be the additional speedup (relative to a processor with forwarding) if we added time-travel forwarding that eliminates all data hazards? Assume that the yet-to-be-invented time-travel circuitry adds 100ps to the latency of the full-forwarding EX stage.

The remaining three problems in this exercise refer to the following latencies for individual pipeline stages. For the EX stage, latencies are given separately for a processor without forwarding and for a processor with different kinds of forwarding.

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IF ID a. 150ps 100ps b. 300ps EX (no FW) 120ps 200ps 300ps EX (full FW) 150ps 350ps EX (FW from EX/MEM only) 140ps 330ps EX (FW from MEM/WB only) 130ps 320ps MEM WB 120ps 100ps 290ps 100ps