Six interface units of the type shown in Fig. 11-2 are connected to a CPU that uses an I/O address of eight bits. Each one of the six chip select (CS) inputs is connected to a different address line. Thus the high-order address line is connected to the CS input of the first interface unit and the sixth address line is connected to the CS input of the sixth interface unit. The two low-order address lines are connected to the RS1 and RS0 of all six interface units. Determine the 8-bit address of each register in each interface.

Fig. 11-2

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Bidirectional data bus Chip select Register select 1/0 read 1/0 write CS RS1 RSO RD WR Bus buffers To CPU 1 1 1 CS RS1 RS0 Register selected 0 1 Timing and control X X 0 0 1 0 1 1 0 1 Internal bus Port A register Port B register Control register Status register To 1/0 device None: data bus in high-impedance Port A register Port B register Control register Status register I/O data I/O data Control Status