Write, compile, and simulate a VHDL description for the state machine diagram shown in Figure 6-38. Use

Question:

Write, compile, and simulate a VHDL description for the state machine diagram shown in Figure 6-38. Use a simulation input that passes through all paths in the state machine diagram, and include both the state and output Z as simulation outputs. Correct and resimulate your design if necessary.

Figure 6-38