Question: Write, compile, and simulate a VHDL description for the state machine diagram shown in Figure 6-38. Use a simulation input that passes through all paths

Write, compile, and simulate a VHDL description for the state machine diagram shown in Figure 6-38. Use a simulation input that passes through all paths in the state machine diagram, and include both the state and output Z as simulation outputs. Correct and resimulate your design if necessary.

Figure 6-38

Default: Z = 0 W Z- (STA W (STB) RESET X.XY (STC) XY Z

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