Write, compile, and simulate a Verilog description for the state machine diagram in Figure 6-38. Use code 00 for state STA, 01 for state STB, and 10 for state STC. Use a simulation input that passes through all paths in the state-machine diagram and include both the state and Z as simulation outputs. Correct and resimulate your design if necessary.

Figure 6-38

Default: Z = 0 W Z- (STA W (STB) RESET X.XY (STC) XY Z