A scan path test circuit of the type shown in Figure 10-8 has three flip-flops, two inputs, and two outputs. One row of the state table of the sequential circuit to be tested is as follows:

For this row of the table, complete a timing chart similar to that shown in Figure 10-9 to show how the circuit can be tested to verify the next states and outputs for inputs 00, 01, and 10. Show the expected Z₁ and Z₂ outputs only at the time when they should be read.

Transcribed Image Text:

Q,*Q2*Q3° Z,Z, Q,Q,Q; | X,X, = 11 10 11 01 00 00 10 01 11 10 01 111 011 010 110 011 00