A nonmaskable interrupt (NMI) is triggered by an input pin to the processor. When the pin is asserted, the current instruction should finish, then the processor should set the Cause register to 0 and take an exception. Show how to modify the multicycle processor in Figures 7.63 and 7.64 to handle nonmaskable interrupts. 

Transcribed Image Text:

EPCWrite IntCause CauseWrite CLK CLK Ox30- 0 Cause 01101 CO Ox28 EN ЕРС 01110 EN 15:11 PCEN RegDst MemtoReg RegWrite PCSrc,0 lorD MemWrite IRWrite ALUSrcA ALUSrcB,, ALUControl, Branch PCWrite 10 CLK CLK CLK CLK CLK SrcA WE WE3 Zero CLK 3128 25:21 PC PC A1 RD1 O Adr A Instr 20:16 00 RD ALUResult ALUOut 01 EN EN A2 RD2 00 Instr/Data 4 01 SrcB ALU Overflow 20:18 10 Memory АЗ Register File 15:11 10 PCJump 11 CLK WD 10 00 11 Ox8000 0180 Data WD3 01 <<2 27.0 Signimm 15:0 Sign Extend 25:0 (jump) Figure 7.63 Datapath supporting mfc0 AB