Design the hazard unit shown in Figure 7.58 for the pipelined MIPS processor. Use an HDL to implement your design. Sketch the hardware that a synthesis tool might generate from your HDL. 

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CLK CLK CLK MRegWriteE MemtoRegE MemWriteE ALUControlE20 MRegWriteM MemtoRegM MemWriteM MRegWriteW MemtoRegW RegWriteD Control MemtoRegD unit MemWriteD ALUControlD20 31:26 Op ALUSrcD ALUSrcE 5:0 Funct RegDstD RegDstE BranchD EqualD PCSrcD CLK CLK CLK CLK 25:21 A1 WE3 V WE STCAE PC' RD1 PCF A. RD InstrD 01 10 ALUOUTM ReadDataW A. RD Instruction 20:16 A2 RD2 SrcBE Data memory A3 memory WD3 Register file WriteDataE WriteDataM WD 25:21 RsD RsE ALUOUTW 20:16 RtD RtE WriteRegEes WriteRegMaa Write RegWo 15:11 RdE RdE SignlmmD SignimmE Sign extend 15:0 <<2 PCPlus4F PCPlus4D PCBranchD ResultW Hazard unit Figure 7.58 Pipelined processor with full hazard handling RegWritew RegWriteM MemtoRegM RegWriteE MemtoRegE FowardBE FowardAE FlushE ForwardBD FonvardAD BranchD StallD StallF