(a) Write Verilog code that describes the logic block shown in Figure 6-1(a). Use the following module:...
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(a) Write Verilog code that describes the logic block shown in Figure 6-1(a). Use the following module:
module Figure6_1a(X_in,Y_in,clk,CE,Qx,Qy,X,Y,XLUT,YLUT);
input[1:4]X_in,Y_in;
input CE,clk;
input[0:15] XLUT,YLUT;
inout X,Y;
output Qx,Qy;
.
.
.
endmodule
Figure 6-1(a)
(b) Write structural Verilog code that instantiates two Figure 6-1(a) block components to implement the 4-to-1 MUX of Figure 6-2. When you instantiate a block, use the actual bit patterns stored in XLUT and YLUT to specify the function generated by each of the LUTs.
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Related Book For
Digital Systems Design Using Verilog
ISBN: 978-1285051079
1st edition
Authors: Charles Roth, Lizy K. John, Byeong Kil Lee
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