(a) Write Verilog code that describes the logic block shown in Figure 6-1(a). Use the following module:

module Figure6_1a(X_in,Y_in,clk,CE,Qx,Qy,X,Y,XLUT,YLUT);

input[1:4]X_in,Y_in;

input CE,clk;

input[0:15] XLUT,YLUT;

inout X,Y;

output Qx,Qy;

.

.

.

endmodule

Figure 6-1(a)

(b) Write structural Verilog code that instantiates two Figure 6-1(a) block components to implement the 4-to-1 MUX of Figure 6-2. When you instantiate a block, use the actual bit patterns stored in XLUT and YLUT to specify the function generated by each of the LUTs.

| X] XX Function | X,]X Function X, generator OX FF X generator FF O CE QX CE So LUT4 M1 , LUT4 X4 Y1 YlY Function Y generator YY Function 13 generator LUT4 QY FF CE QY FF CE So M2 YA LUT4 Figure 6-2: Highlighting Paths for a 4-to-1 MUX