An inhibited toggle flip-flop has inputs I₀, I₁, T, and Reset and outputs Q and QN. Reset is active high and overrides the action of the other inputs. The flip-flop works as follows: If I₀ = 1, the flip-flop changes state on the rising edge of T; if I₁ = 1, the flip-flop changes state on the falling edge of T. If I₀ = I₁ = 0, no state change occurs (except on reset). Assume the propagation delay from T to output is 8 ns and from reset to output is 5ns.

(a) Write a complete Verilog description of this flip-flop.
(b) Write a sequence of simulator commands that will test the flip-flop for the input sequence I₁ = 1, toggle T twice, I₁ = 0, I₀ = 1, toggle T twice.