Consider the Verilog code
module example(a,b);
input[1:0] a;
output[1:0] b;
reg[1:0] b;
always @(a)
begin
case(a)
0: b 5 2’d3;
1: b 5 2’d2;
2: b 5 2’d1;
3: b 5 2’d1;
endcase
end
endmodule

(a) Show the hardware you would obtain if you synthesize the foregoing Verilog code without any optimizations. Explain your reasoning.
(b) Show optimized hardware emphasizing minimum area. Show the steps and the reasoning by which you obtained the optimized hardware.