The structural Verilog code that follows is a 2-input NOR gate with the rise/fall time defined as parameters.

module NOR2(a, b, c);
parameter Trise = 3;
parameter Tfall = 2;

parameter load = 1;
input a, b;
output reg c;
wire nor_value;
assign nor_value = ~(a | b);
always @(nor_value)
begin
if(nor_value == 1'b1)
#(Trise + 3*load) c = 1'b1;
else
#(Tfall + 3*load) c = 1'b0;
end
endmodule
module NOR2_TEST(in1, in2, in3, in4, out1, out2);
input in1, in2, in3, in4;
output out1, out2;
NOR2 U1 (in1, in2, out1);
/*
place for your new code
*/
endmodule

(a) Instantiate NOR2 (U2) by using the parameter map method (Trise = 5, Tfall = 4, load = 3).
(b) Use the defparam to pre-define the timing values and instantiate NOR2 (U3), which has rise time = 4, fall time = 3, and load = 2.
(c) What are the rise time, fall time, and fan-out time of U1?
(d) What are the rise and fall delays of NOR2 (U2)?