Question: Write a Verilog model for an N-bit comparator using an iterative circuit. In the module, use the parameter N to define the length of the

Write a Verilog model for an N-bit comparator using an iterative circuit. In the module, use the parameter N to define the length of the input bit vectors A and B. The comparator outputs should be EQ = 1 if A = B, and GT = 1 if A > B. Use a for loop to do the comparison on a bit-by-bit basis, starting with the high-order bits. Even though the comparison is done on a bit-by-bit basis, the final values of EQ and GT apply to A and B as a whole.

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