Question: Write a Verilog model for a 74HC192 synchronous 4-bit up/down counter. Ignore all timing data. Your code should contain a statement of the form always

Write a Verilog model for a 74HC192 synchronous 4-bit up/down counter. Ignore all timing data. Your code should contain a statement of the form always @(DOWN,UP, CLR, LOADB).

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