Modify the VHDL code in Figure 6-24 to create a 4-bit parallel adder. Figure 6-24 900260 GAWNH

Modify the VHDL code in Figure 6-24 to create a 4-bit parallel adder.

Figure 6-24

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900260 GAWNH 2 4 ENTITY fig6_24 IS PORT ( 10 a b S : IN INTEGER RANGE 0 TO 255; :IN INTEGER RANGE 0 TO 255; :OUT INTEGER RANGE 0 TO 511 6 ); 7 END fig6_24; ARCHITECTURE parallel OF fig6_24 IS 11 BEGIN 12 13 END parallel; s<= a + b; 8-bit augend 8-bit addend -- 9-bit sum -- add operands