1. (30 Points) Consider the code segment in RISC-V which is similar to LEGv8 fld fld fmult fo, 0(x0) f2, 0(x2) f2, f2, fo f2, 0(x2) load fo from address 0+x0 ; load f2 from address 0+x2 Loop fsd addwi x2, x2,8 suhwi x4, x3, x2 ;store x2 at address 0+x2 ;x2 x2+8 x4 x3- x2 x4, xO, loop branch to loop if x4lE O bne Assume the initial value of x3 is x2 + 64. Assume x0 0 and x2-16, and the memory contains 16 7.0 32 5.0 40 3.0 64 5.0 72 8.0 80 7.0 24 48 56 4.0 1.0 9.0 1.0 2.0 3.0 16 24 32 40 48 56 64 72 80 The cache size is 64 bytes and the block size is 16 bytes. Display the content of memory, cache hit or miss status, and the content of cache as the loop executes, assuming the cache is direct mapped, with write through and no write allocate Repeat Part (a) assuming cache is a 2-wayset associative, with FIFO replacement policy, and write back, and write allocate a) b) 1. (30 Points) Consider the code segment in RISC-V which is similar to LEGv8 fld fld fmult fo, 0(x0) f2, 0(x2) f2, f2, fo f2, 0(x2) load fo from address 0+x0 ; load f2 from address 0+x2 Loop fsd addwi x2, x2,8 suhwi x4, x3, x2 ;store x2 at address 0+x2 ;x2 x2+8 x4 x3- x2 x4, xO, loop branch to loop if x4lE O bne Assume the initial value of x3 is x2 + 64. Assume x0 0 and x2-16, and the memory contains 16 7.0 32 5.0 40 3.0 64 5.0 72 8.0 80 7.0 24 48 56 4.0 1.0 9.0 1.0 2.0 3.0 16 24 32 40 48 56 64 72 80 The cache size is 64 bytes and the block size is 16 bytes. Display the content of memory, cache hit or miss status, and the content of cache as the loop executes, assuming the cache is direct mapped, with write through and no write allocate Repeat Part (a) assuming cache is a 2-wayset associative, with FIFO replacement policy, and write back, and write allocate a) b)