(30 Points) Consider the code segment in RISC-V which is similar to LEGv8

fld f0, 0(x0) ; load f0 from address 0+x0

Loop: fld f2, 0(x2) ; load f2 from address 0+x2

fmult f2, f2, f0 ; f2 = f2 * f0

fsd f2, 0(x2) ; store x2 at address 0+x2

addwi x2, x2, 8 ; x2 = x2 +8

subwi x4, x3, x2 ; x4 = x3 x2

bne x4, x0, loop ; branch to loop if x4!= 0

Assume the initial value of x3 is x2 + 64. Assume x0 =0 and x2=16, and the memory contains:

M[0]	M[8]	M[16]	M[24]	M[32]	M[40]	M[48]	M[56]	M[64]	M[72]	M[80]	M[88]
4.0	1.0	7.0	9.0	5.0	3.0	1.0	2.0	5.0	8.0	7.0	3.0

0 8 16 24 32 40 48 56 64 72 80

The cache size is 64 bytes and the block size is 16 bytes. Make a table similar with Example 5 in Lecture slides.

Display the content of memory, cache hit or miss status, and the content of cache as the loop executes, assuming the cache is direct mapped, with write through and no write allocate.

Repeat Part (a) assuming cache is a 2-way set associative, with FIFO replacement policy, and write back, and write allocate.