1. Consider the code segment in RISC-V which is similar to LEGv8 fid f0, 0(x0) ; load f0 from address 0+x0 f2, 0(x2) store x2 at address 0+x2 x4, x0, loop ;branch to loop if x4! 0 Loop fld f2, 0(x2) ; load f2 from address 0+x2 fmultf2, f2, fo f2 f2 fo fsd addwi x2, x2, 8 x2-x2+8 bwi x4, x3, x2 X4 x3 - x2 Assume the initial value of x3 is x264. Assume x0 0 and x2-16, and the contains: MIOI M[8] | M[16] | M[24] M[32] | M[40] M[48] | M[56] MI64] | M(72] |MI801 |MI88] 4.0 1.0 7.0 9.0 5.0 3.0 1.0 2.0 5.0 8.0 7.0 3.0 16 24 32 40 48 56 64 72 80 The cache size is 64 bytes and the block size is 16 bytes. Make a table similar with Example 5 in Lecture slides a) Display the content of memory, cache hit or miss status, and the content of cache as the loop executes, assuming the cache is direct mapped, with write through and no write allocate b) Repeat Part (a) assuming cache is a 2-way set associative, with FIFO replacement policy, and write back, and write allocate 1. Consider the code segment in RISC-V which is similar to LEGv8 fid f0, 0(x0) ; load f0 from address 0+x0 f2, 0(x2) store x2 at address 0+x2 x4, x0, loop ;branch to loop if x4! 0 Loop fld f2, 0(x2) ; load f2 from address 0+x2 fmultf2, f2, fo f2 f2 fo fsd addwi x2, x2, 8 x2-x2+8 bwi x4, x3, x2 X4 x3 - x2 Assume the initial value of x3 is x264. Assume x0 0 and x2-16, and the contains: MIOI M[8] | M[16] | M[24] M[32] | M[40] M[48] | M[56] MI64] | M(72] |MI801 |MI88] 4.0 1.0 7.0 9.0 5.0 3.0 1.0 2.0 5.0 8.0 7.0 3.0 16 24 32 40 48 56 64 72 80 The cache size is 64 bytes and the block size is 16 bytes. Make a table similar with Example 5 in Lecture slides a) Display the content of memory, cache hit or miss status, and the content of cache as the loop executes, assuming the cache is direct mapped, with write through and no write allocate b) Repeat Part (a) assuming cache is a 2-way set associative, with FIFO replacement policy, and write back, and write allocate